This invention relates to CCD imaging arrays.
The invention is particularly applicable to two-phase clocked CCDs, for example, of the frame transfer type or the full frame type. The invention is concerned with extending the dynamic range of such CCDs.
Referring to FIG. 1, which is a schematic view of a frame transfer CCD, charge is collected in an image region 1 consisting of a rectangular array of pixels, and then fed to a store region 2 also having a rectangular array of pixels. The integration takes place in the image section for one field period, typically just under 1/50th second in the UK and typically just under 1/60th second in the US. The image is then transferred rapidly from the image section to the store section, line by line, but during a substantially shorter period, known as the frame transfer period. This is done by applying clocked voltages typically designated IØ1 and IØ2 to pairs of electrodes in the image region and clocked voltages SØ1 and SØ2 to pairs of electrodes in the store region. Then, while the next image is being built up on the image section, the image in the store section is clocked out line-by-line into an output register 3. Successive lines are clocked along the output register in serial fashion, and charge multiplication may take place in a multiplication register 4 connected as a linear extension to the output register, such as, for example described in our U.S. Pat. No. 6,444,968.
Optionally, and ideally, a shutter disperses or, better, blanks off the optical signal to the CCD during the frame transfer period to prevent frame shift smear. This may be achieved in practice with a liquid crystal arrangement such as a liquid crystal polymer (LCP) shutter, or a mechanical arrangement such as a rotating disc with a blade to obscure the CCD.
Typically an anti-blooming drain is provided whose potential is set so as to trap and discharge any build-up of signal within any pixel or group of pixels that would otherwise spill over into adjacent pixels and give blooming to the image in that area. This provides an artificial white clip. The smallest useable signal is a finite measure which exceeds the noise floor of the readout system. The ratio of the clipped white value to the useable low level is known as the dynamic range of the sensor, and is often expressed in terms of “stops”, dB or octaves.
The operation of the anti-blooming drain will now be described with reference to FIGS. 2 to 6. FIG. 2 shows a fragment 5 of the image region 1 of the frame transfer CCD of FIG. 1 on an enlarged scale, FIG. 3 is a section taken on the lines 3-3 in FIG. 2, and FIGS. 4 to 6 show the potential under the electrodes shown in FIG. 3 in various operating states, with potential increasing in the negative direction as seen in the drawing.
FIG. 2 shows a fragment of a column of pixels p1 to p3. Laterally, the pixels are defined by isolation regions which incorporate anti-blooming structures. The anti-blooming structures comprise of drains 8, 9 with barrier regions 6, 7, 10, 11 on either side. The drains are joined to a common connection, typically at the ‘top’ of the image section (remote from the storage section), and supplied by a suitable voltage source or clock pulse generator. The drains are typically produced by a relatively high dose ion implantation to give high conductivity which permits them to absorb large quantities of excess signal charge. The barriers 6, 7, 10, 11 on either side of the drains may be formed by a relatively low dose ion implantation, by an additional gate electrode which underlies the CCD transfer clock electrodes, or by a combination of the two. The barriers on opposite sides of a drain may be different in type and in ‘height’ such that only those on one side of the drain are active in the anti-blooming process. If gate electrodes are used they are also typically joined at the ‘top’ of the image section and supplied by a suitable voltage source or clock pulse generator. To minimise the fraction of the device active area occupied by the drain structure, symmetrical drains may be incorporated between alternate pairs of columns, with conventional channel stop regions between the other pairs, such that each column is adjacent to one drain and one channel stop.
The pixels p1, p3 and p5 are in rows (or lines) in the store region, and correspond to Display lines 1, 3 and 5 in FIG. 5. Each row of pixels is associated with a pair of electrodes, for example, e1, e2.
Under each electrode e1 to e6, there is a respective doped implant region d1 to d6, which regions are essential to enable the CCD to operate in a two-phase manner. The implant regions define regions of low potential which separate potential wells w1 to w6 and enable charge to be built up (in two wells) for each individual pixel. Alternative techniques to produce the regions of low potential (e.g. variations in dielectric thickness) are also known and may be used with this invention.
In the standard operating mode, photo-generated charge is collected in the image section of the CCD during the integration periods with both clock phases Ø1 and Ø2 held in their low state (FIG. 4), so that the potential of the wells w1 to w6 is low (but not as low as that under the implants d1 to d6). Charge accumulates in the wells (FIG. 4). This low state is typically at a potential sufficiently negative with respect to the CCD substrate that the silicon surface in the CCD buried channel becomes inverted and a layer of holes ‘pins’ the surface potential to the substrate bias voltage. The presence of these holes at the surface significantly reduces dark current generation by ‘surface states’ at the interface between the silicon and the silicon dioxide gate dielectric. This is a well-known technique described as pinned, multi phase pinned (MPP) or inverted mode operation (IMO).
The anti-blooming drains 8, 9 absorb photo-generated charge signals which exceed a designated storage capacity of the wells w1 to w6. This prevents such charge packets spreading beyond their regions of generation and corrupting adjacent parts of the image. The anti-blooming structures include barriers 6, 7 which define the signal level at which charge spills to the anti-blooming structure. Hence, during the integration period, charge cannot build up beyond a designated level in the wells w1 to w6 (FIG. 4), as excess charge drains over the barriers 6, 7 to the anti-blooming structure.
During the subsequent frame transfer period, the voltages Ø1, Ø2 applied to the electrodes e1 to e6 are alternately pulsed high. Referring to FIG. 5, on the first cycle, the voltages Ø2 on electrodes e1, e3, e5 are pulsed high, while the voltages Ø1 on electrodes e2, e4, e6 are pulsed low, and this results in the charge in pairs of wells w1, w2; w3, w4; and w5, w6 being combined to form Display lines 1, 3, 5 respectively. On the next clock cycle, voltages Ø1 are pulsed high while voltages Ø2 are pulsed low, which transfers the combined charges to the well to the right as seen in FIG. 5, for example, the charge stored beneath electrode e5 is transferred to below e4, the charge beneath e3 is transferred to below e2, etc. Ø1 and Ø2 in both image and store section are together clocked high alternately until the entire charge pattern from the image section has been transferred to the store section.
CCDs for TV imaging need to produce two interlaced fields to produce one frame, and the required interlace operation is achieved by different pairing of the charge collected under adjacent electrodes in the odd and even fields. This is achieved by taking a different one of the voltages, Ø1 and Ø2 high at the start of alternate frame transfer operations. Comparing FIG. 6 with FIG. 5, it can be seen the charge in pairs of wells w2 and w3 is combined to produce Display line 2, and the charge in pairs of wells w4 and w5 is combined to produce Display line 4.
One known technique for enhancing the dynamic range involves modifying the storage capacity of the image section during the integration period by modulating the potentials applied to the anti-blooming drain or gate (U.S. Pat. No. 5,276,520). Referring to FIG. 7, during a first portion (90%, for example) of the integration period the storage capacity of the CCD image section is reduced to a level (50% for example) below its normal capacity by effectively lowering the barrier between the storage site and the anti-blooming drain. During the second portion (10%) of the integration period the full storage capacity (100%) is restored. The relationship between these values is determined by the timing and amplitude of the voltage modulation applied to the anti-blooming structure. The advantage of this can be seen by reference to FIG. 7.
If there were no clipping, and signal levels I1 and I2 were received, both would reach the capacity of the well within the integration period, and the CCD could not detect any difference in the intensity of the incoming signals. By clipping the signal for a part of the integration period, the CCD is able to distinguish between very high illumination (dashed line) I1, high illumination (chain dashed line) I2, medium illumination (dotted) I3, and low illumination (solid line) I4.
However, there are two disadvantages with this known technique. Firstly, the method requires additional drive waveforms to be applied to the anti-blooming structure. The voltages required for these waveforms are generally different to the standard clock levels and the required stability may be higher than normally required for a clock pulse in order to maintain a consistent transfer function. Secondly, it is known that, in many cases, when the capacity of a pixel is reduced by modulating an anti-blooming structure, the uniformity of the clipping level exceeds an acceptable margin. Such non-uniformity would add additional noise to all signal levels which were clipped for any part of the integration period.
Another technique for increasing the dynamic range in an interline transfer CCD has been proposed (U.S. Pat. No. 4,302,779). Excess signal charge in the individual photosensitive elements is drained as a non-information signal using pulse signals of carefully controlled amplitude.